The present invention relates generally to testing integrated circuit devices, and more particularly, to providing reflection control during transmission line pulse (TLP) and very-fast transmission line pulse (VF-TLP) testing of electrostatic discharge (ESD) protection devices on a wafer.
TLP and VF-TLP testing of an ESD protection device, which may be included as part of an integrated circuit device under test (DUT), is typically performed by using a high-voltage power supply to charge a transmission line at a predetermined voltage level. A switch or relay is then closed to connect the charged transmission line to the DUT via a pulse delivery cable. The transmission line discharges into the DUT by delivering pulses (e.g., TLP, VF-TFLP) through the pulse delivery cable to the DUT. A reflection of the pulses from the DUT usually occurs because of an impedance mismatch that exists between the ESD protection device or the DUT and the pulse generator (i.e., the high-voltage power supply, transmission line, switch and pulse delivery cable) that delivers the pulses. The reflection typically causes a large percentage of the incident pulse energy to travel back to the pulse generator. Since the DUT typically has a lower impedance than the pulse generator, the voltage pulse reflection polarity from the DUT is typically inverted from the incident pulse. The pulse generator, which can be a TLP or VF-TLP pulse generator, will cause a re-reflection of the reflected pulse energy from the pulse generator back to the DUT with the same polarity as the reflection from the DUT. This re-reflection will stress the DUT with re-reflected pulse energy that is typically in an inverted polarity from the polarity of the DUT that enables it to protect against voltage transients. Stressing the DUT with a reverse or inverted polarity will eventually cause it to fail and result in erroneous current and voltage measurement characterizations of the ESD protection device.